The disclosure is generally directed to preserving an invalid global domain indication for a cache line and, more particularly, to techniques for preserving an invalid global domain indication when installing a shared cache line in a cache.
Modern microprocessors typically include entire storage hierarchies (caches) integrated into a single integrated circuit. For example, one or more processor cores that include level 1 (L1) instruction and/or data caches are often combined with a shared on-chip level 2 (L2) cache and may be combined with a shared on-chip level 3 (L3) cache. Caches in a cache hierarchy typically include cache directories that, among other functions, maintain one or more cache coherency states for each cache line in a cache array.
An invalid global (IG) state is a cache coherency state that indicates: an associated memory block (e.g., a cache line) in a cache array is invalid; an address tag in a cache directory is valid; and a copy of the memory block identified by the address tag may possibly be cached in another node in a coherency domain (which includes a group of nodes in which coherency is maintained). The IG state may be formed in a lower level cache in response to the lower level cache providing a requested memory block to a requestor in another node of a coherency domain in response to an exclusive access request. The IG state may, for example, only be formed in a node of a coherency domain that includes a lowest point of coherency (LPC) for the memory block. In such embodiments, some mechanism (e.g., a partial response by the LPC and subsequent combined response) is typically implemented to indicate to a cache sourcing a requested memory block that the LPC is within its node of the coherency domain. In other embodiments that do not support the communication of an indication that the LPC is local, an IG state may be formed any time that a cache sources a memory block to a remote node in the coherency domain in response to an exclusive access request.
An LPC may, for example, be a memory device or an input/output (I/O) device that serves as a repository for a memory block. In the absence of a highest point of coherency (HPC) for a memory block, an LPC stores a true image of the memory block and has authority to grant or deny requests to generate an additional cached copy of the memory block. For a typical request in a data processing system, an LPC corresponds to a memory controller for main memory that stores a referenced memory block. In general, an HPC is a uniquely identified device that caches a true image of a memory block (which may or may not be consistent with the corresponding memory block at the LPC) and has the authority to grant or deny a request to modify the memory block. An HPC may also provide a copy of a memory block to a requestor in response to an operation that does not modify the memory block.